A Digital PLL (DPLL) is a PLL that is mostly digital; it does not have an analog loop filter or analog charge-pump circuits; these sub-components are replaced with digital equivalents.
Wide Range and Programmability: A digital PLL is much easier to design in applications with a wide range of reference frequencies and output frequencies; the dynamics of the loop filter automatically track with the reference frequency. This should be compared with an analog approach where the analog loop filter must be ‘digitally trimmed’ for different bandwidths and reference frequencies, and the tuning range is limited. In addition, a highly-programmable digital approach can be digitally adjusted for many different application requirements; this allows for a One Size Fits All, minimizing both costs and support complexities. The programmability of the IP block includes output impedance, loop bandwidth, output division ratio, VCO load capacitance, input reference amplifier type, current bias levels, etc.
Predictability: the DPLL is primarily composed of digital logic circuits which are highly predictable especially in sub-micron processes. What you simulate is what you get. Digital circuits are not affected (to the same degree) by analog issues such as leakage currents through loop capacitors, offset voltages due to transistor mismatches, substrate noise, reference feedthrough, etc. Predictability is critical as one goes to 40nm and smaller technologies in order to eliminate iterating on tape-outs.
Porting: porting a PLL to a new technology is much faster and involves much less risk for a Digital PLL; most of the analog-like circuits are realized using only I/O transistors, and these seldom need to be changed during the porting process; digital logic needs to be ported, but this is fast and low risk.
Size: because the loop-filter, analog charge pumps, and anlaog voltage regulators, have been eliminated, the size is considerably smaller than analog PLLs; this is especially true as one goes to smaller technologies.
has a number of DPLL's optimized for different technologies
and processes. The DPLL's are completely integrated and
don't require any off-chip components. They can all be
programmed using either a serial SPI bus, or a parallel bus;
both are included.
This DPLL is optimized for high frequency and supports 0.5-7.5 GHz in TSMC's 40G
This DPLL is similar to the 40G DPL, but is optimized for TSMC's 40LP process and during the port it was modified for significantly improved long-term jitter.
This DPLL was optimized for low power (5 mW), and extremely low area in TSMC's 28HPM process (0.06mm2)
This DPLL is optimized for extremely low frequency input references having excessive jitter. It has an innovative dual-loop architecture (second loop is low frequency digital - no power increase and low risk) that does not have the inherent trade-off between minimizing self-generated jitter versus input reference jitter of single-loop architectures. It supports extremely large oscillator/reference frequency ratios.
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