Granite Semicom has just received first silicon of its totally-integrated (no off-chip components) Clock-Driver and Clock-Multiplying-Unit IP block with fractional-N division capability. This High-Speed Digital PLL is intended for applications such as the CMU in a SERDES block at data rates as high as 12.5 Gbs (and higher), and for clock-driver applications where the frequencies are not integrally related. This IP block contains a digital phased-lock-loop, plus an integrated voltage and current reference, a variety of input amplifiers (single-ended and differential, dc and ac-coupled), a number of programmable dividers, a serial interface for programming, and a high-speed 50 ohm driver capable of driving off-chip at full-speed. The feedback divider in the PLL can be programmed to be non-integer to allow for Fractional/N applications, which allows for non-integer output frequency to reference frequency ratios. The specification is for the High-Speed Digital PLL (HSDPLL) to operate between 0.5GHz and 6.25GHz over process corners and between -40 and 125 degrees celsius; the first measured sample locks for output frequencies between 0.144GHz and 10.8GHz, dissipates 32 mw (at 5GHz output), and requires a 0.11 mm^2 area (not including pads and the output driver). Jitter measurements are on-going, but first off-chip measurements (after the output driver and 2cm of PCB trace) indicate total rms jitter (random and deterministic) of 1-2 ps accumulated jitter for a 5GHz output frequency, depending on the loop-bandwidth chosen.

Other examples of IP building blocks currently being developed by GSC include a generic analog calibration engine that incorporates a high-quality band-gap voltage reference, a highly-configurable error-detection-circuit, arbitrary-accuracy trimming DAC (or DAC's), and a digital state controller which adapts to minimize the calibration error. The distributed approach is efficient and allows for extensive calibration with minimal costs.

Other blocks being developed include A/D converters, D/A converter, drivers, filters, etc. GSC has capabilities and previous experience to develop practically any block needed by customers.

All blocks being developed use a new design flow that allows for  extensive customization to meet individual customer's requirements at minimal additional expense. The flow is based on technology-independant approaches and builds in easy porting to additional technology nodes.

GSC has a unique approach that allows for extremely long battery life-times in applications where intermittent operation is expected; the power of always-on monitoring circuits are kept exceptionally low (a few tens of uW's depending on application), and wake-up to full-operational lock times are greatly minimized. GSC will help customers optimize their system and circuit block designs, and accurately simulate their systems (a  demanding task in this application). GSC has a large number of ready-to-go building blocks optimized for IOBat (Intermittent-Operation Battery-powered applications), and is willing to customize existing, and design new, blocks.

GSC also offers system design services for mixed-mode analog/digital approaches and will work as the system integrator to incorporate it's IP blocks with IP blocks from other vendors and be responsible for all of them working together correctly. In the event of problems, GSC will manage an efficient debugging phase with the goal being not laying blame, but doing whatever is necessary to get the customer's IC to market in the least time possible; this was an area that Dr. Martin's previous company excelled at based on methodology's invented by him. GSC takes these methodologies to a new level.